Error (suppressible): ../../altera_rs_ser_dec_191/sim/rs2_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "in0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated. - Error (suppressible): ../../altera_rs_ser_dec_191/sim/rs2_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "in0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated. Description Due to a problem with the Reed Solomon II Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, you may observe the above error when simulating the VHDL simulation model in Modelsim* software. Resolution To work around this problem, you can use the Verilog simulation model. Custom Fields values: ['novalue'] Troubleshooting 1509022659 False ['IP Reed-Solomon Encoder/Decoder II IP-RSCODECII'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 20.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']