Error(16186): Can't elaborate top-level user hierarchy: "VHDL info at pcie_example_design.vhd(1337): back to vhdl to continue elaboration" - Error(16186): Can't elaborate top-level user hierarchy: "VHDL info at pcie_example_design.vhd(1337): back to vhdl to continue elaboration" Description Due to a problem in the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example version 18.1 , you may observe this error when the "Generate HDL format" option is set to VHDL. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software version 18.1 set the "Generate HDL format" option to Verilog. This problem has been fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.1 Custom Fields values: ['novalue'] Troubleshooting 2205695476 False ['Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']