Why do I get project directory/<VIP_component>.vhd (17): near "EOF": syntax error - Why do I get project directory/<VIP_component>.vhd (17): near "EOF": syntax error Description When running the EDA RTL simulation for VIP design within Quartus ® II, and you may get the above error in Modelsim. In order to workaround this issue, please open the <SOPC_project_name>_run_msim_rtl_verilog.do (located at “Project directory”\simulation\modelsim\) and remove the <VIP_component>.vhd from this file. After that, please execute the <SOPC_project_name>_run_msim_rtl_verilog.do file within the Modelsim. The <VIP_component>.vhd is actually not required for RTL simulation. Therefore, we can manually remove it in order to resolve the issue. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']