Why is the o_rx_pcs_fully_aligned signal not asserted in my F-tile Ethernet Intel® FPGA Hard IP simulation in Questa* Intel® FPGA Edition when IEEE* 1588 PTP, or Auto-negotiation (AN) and Link training (LT), or both features are enabled? - Why is the o_rx_pcs_fully_aligned signal not asserted in my F-tile Ethernet Intel® FPGA Hard IP simulation in Questa* Intel® FPGA Edition when IEEE* 1588 PTP, or Auto-negotiation (AN) and Link training (LT), or both features are enabled? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, the F-Tile Ethernet Intel® FPGA Hard IP does not configure the Questa* Intel® FPGA Edition simulation environment properly. The F-Tile Ethernet Intel® FPGA Hard IP requires macro definition support for environment setup, which the Questa* Intel® FPGA Edition simulator doesn't have. As a result, the o_rx_pcs_fully_aligned signal is not asserted, and the simulation cannot complete the RX reset sequence. Resolution You can run F-Tile Ethernet Intel® FPGA Hard IP PTP simulations with Questa* Intel® FPGA Edition simulation OEM starting with Intel® Quartus® Prime Pro Edition Software version 22.1. Custom Fields values: ['novalue'] Errata 1509630629 True ['F-Tile Ethernet Multirate IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']