Timing report with signal names - Timing report with signal names Hi, I have a question regarding Timing Analyser: Is there a possibility to show all signals names in the detailed timing summary? My starting node is: separator|prev_parser_state_d[0][2]~RTM_6|q it goes through a lot of combout*** named cells. I would prefer showing the signal/port names instead of the physical resource used in FPGA. Is there a configuration to switch this setting? Best regards, Michael Replies: Re: Timing report with signal names Short answer: no. Longer answer: timing analysis with SDC is based on physical nodes in the design. What you're seeing is the start of a path specified as the q output of a register, part of the get_pins collection in the SDC timing netlist. When you look at a timing report in the timing analyzer, you can always cross-probe the node to other tools in Quartus, so you can see where this node is in your design.