JTAG USER1 register on Max 10 - JTAG USER1 register on Max 10 We instantiated a JTAG USER1 register in a Max II device by using this built-in component (VHDL): component maxii_jtag PORT ( tms : in std_logic; tck : in std_logic; tdi : in std_logic; tdouser : in std_logic; tdo : out std_logic; tmsutap : out std_logic; tckutap : out std_logic; tdiutap : out std_logic; shiftuser : out std_logic; clkdruser : out std_logic; updateuser : out std_logic; runidleuser : out std_logic; usr1user : out std_logic); end component; We just needed a couple more lines of VHDL code to instantiate our USER1 register. We are converting it to a Max 10 device, but this component does not exist. How do we do this (simply) with a Max 10 device? Replies: Re: JTAG USER1 register on Max 10 Thanks! That worked. I should have figured out that fiftyfivenm_jtag would go with the Max 10 device, since it uses 55nm silicon. Replies: Re: JTAG USER1 register on Max 10 Please use the fiftyfivenm_jtag component for MAX 10. Refer Intel MAX 10 FPGA Configuration User Guide: https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html Regards Replies: Re: JTAG USER1 register on Max 10 Please use the fiftyfivenm_jtag component for MAX 10. Reference: https://www.intel.com/content/dam/altera-www/global/en_US/uploads/5/5f/MAX10_JTAG_Secure_Unlock_UG.pdf Regards Replies: Re: JTAG USER1 register on Max 10 The problem is that I'm using a very small CPLD devices, and this 'virtual jtag' function adds a lot of unnecessary logic that eats up space I need in the device. I'm trying to do something really simple in a very simple device. I'm just trying to add a USR register. Nothing else. The 'component maxii_jtag' gave me exactly what I wanted, even signals the 'virtual jtag' function doesn't give, such as a clock for shifting the user register (clkdruser). I could create this from the 'virtual jtag' outputs, but that is even more logic I'd have to add. Using the 'virtual jtag' function makes the code more complicated than it needs to be and adds a bunch of extra logic I don't need or want. Almost every CPLD/FPGA has a function like the " component maxii_jtag". All of these exist: component arriaii_jtag component arriaiigz_jtag component arriav_jtag component arriavgz_jtag component cyclone_jtag component cyclone10lp_jtag component cycloneii_jtag component cycloneiii_jtag component cycloneiiils_jtag component cycloneiv_jtag component cycloneive_jtag component cyclonev_jtag component fiftyfivenm_jtag component maxii_jtag component maxv_jtag component stratix_jtag component stratixgx_jtag component stratixii_jtag component stratixiigx_jtag component stratixiii_jtag component stratixiv_jtag component stratixv_jtag component twentynm_jtagblock component twentynm_jtag component twentynm_hps_interface_jtag Only component max10_jtag seems to be missing--the very one I want! Replies: Re: JTAG USER1 register on Max 10 Hi Thomas, The Virtual JTAG IP can help you. Here is the user guide. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf Regards. - 2021-02-09