Introduction to the 28-nm Hard IP for PCI Express - 37 Minutes Are you new to using the Hard IP for PCI Express® found in Cyclone® V, Arria® V and Stratix® V devices? If so, then you should start with this course. In this class, you will learn the capabilities and features of the Hard IP for PCI Express to see why it is the right solution for your PCI Express design. You will learn the core variations that are available to help you decide which variation is the best based on your design requirements. Course Objectives At course completion, you will be able to: Describe the basic and advanced features of the Hard IP for PCI Express block found in select Altera® 28nm devices Select between the different Hard IP for PCI Express core variations based on performance and required features Skills Required Some understanding of the PCI Express Protocol specification is helpful, but not required Familiarity with common high-speed transceiver architecture or viewing the following transceiver basics course or attending the Building Gigabit interfaces in Altera® transceiver devices Familiarity with FPGA/CPLD design flow Familiarity with the Quartus design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCIINTRO. FPGA_OPCIINTRO. <p>Introduction to the 28-nm Hard IP for PCI Express</p>