How to connect clock to pipe_pclk when using Intel® Arria® 10 FPGA Transceiver Native PHY in PIPE mode? - How to connect clock to pipe_pclk when using Intel® Arria® 10 FPGA Transceiver Native PHY in PIPE mode? Description tx_clkout is preferable for pipe_pclk . Its frequency will change automatically according to Gen1/Gen2/Gen3 speed and data width configuration. Resolution Depending on the link width configuration, always use the middle tx_clkout to minimize the clock skew between channels. For instances: x1 and x2 --> use tx_clkout[0] x4 --> use tx_clkout[1] or tx_clkout[2] x8 --> use tx_clkout [3] or tx_clkout[4] The hclk_out port of Native PHY can be left floating. It is basically a feed through version of the hclk_in supplied by the Tx phase-locked loop (PLL). Typically, this clock is not used because its frequency is fixed. It's only used if the 3rd party intellectual property (IP) requires a fixed frequency clock. Custom Fields values: ['novalue'] Troubleshooting FB: 517283; False ['Transceiver Native PHY Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']