Can I perform back to back writes to the Intel® Stratix® 10 and Intel Agilex® 7 FPGA E-Tile Transceiver Native PHY Intel FPGA IP ? - Can I perform back to back writes to the Intel® Stratix® 10 and Intel Agilex® 7 FPGA E-Tile Transceiver Native PHY Intel FPGA IP ? Description Yes, you can perform back to back writes to the Intel® Stratix® 10 and Intel Agilex® 7 FPGA E-Tile Transceiver Native PHY Intel FPGA IP ? The Intel E-Tile Transceiver PHY User Guide states the following in chapter “ 9.5. RS-FEC Registers . “ The delay between RS-FEC register reads should be at least10 μs .” There is no such requirement for register writes. Resolution This information will be added to a future version of the Intel E-Tile Transceiver PHY User Guide. Custom Fields values: ['novalue'] Troubleshooting 1808578912 False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.2 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']