Errors: Associated clock clock_sink must be a interface of this component. - Errors: Associated clock clock_sink must be a interface of this component. Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.4 and earlier, you may see errors below even though you have assigned an associated clock to the Avalon® Memory Mapped interface when creating the component using the component editor tool. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software version 19.4 and earlier, follow the steps below. Assign associated clock/reset to the Avalon® MM interfaces in component editor tool Ignore the error information you may see Click File > Save Click Finish... Reopen the component (*_hw.tcl) and make sure there is no errors in component editor tool This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507778405 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']