Why does the H-Tile Hard IP for Ethernet FPGA IP Core failed to generate the design example? - Why does the H-Tile Hard IP for Ethernet FPGA IP Core failed to generate the design example? Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.2, the H-Tile Hard IP for Ethernet FPGA IP Core will fail to generate a design example if the Target Development Kit is set to NONE. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.2, set the T arget Development Kit to the kit featuring the device closest to your project's device. This problem is fixed starting with the Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1409514900 True ['H-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']