Why do Arria® 10 and Cyclone® 10 GX PCIe* Hard IPs not allow a memory write completion TLP to pass a memory read TLP? - Why do Arria® 10 and Cyclone® 10 GX PCIe* Hard IPs not allow a memory write completion TLP to pass a memory read TLP? Description There is a design limitation in the Arria® 10 and Cyclone® 10 GX PCIe* Hard IPs which do not have a bypass buffer to store memory read TLPs. If there is no credit to send any memory read TLPs, these TLPs will stay in the queue, which causes memory write completion TLPs to be head-of-line blocked. Arria® 10 and Cyclone® 10 GX PCIe* Hard IPs do not allow any memory write completion TLP to pass a memory read TLP because the Hard IP does not have a bypass buffer to put memory read TLPs aside and give way to memory write completion TLP to go ahead of these memory read TLPs. Resolution There is no workaround for this problem. The user application and software should be aware of the limitation and take care of this scenario. This problem will not be fixed in any future versions of the IP software release. Custom Fields values: ['novalue'] Troubleshooting FB: 561131; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']