Stratix 10 FPGA H-Tile Hard IP for Ethernet - The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS)… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix 10 FPGA H-Tile production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard. The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation. The 100GBASE-R4 Ethernet channel maps to four 25.78125 Gbps links. The FPGA serial transceivers are compliant with the IEEE 802.3-2015 High Speed Ethernet Standard CAUI-4 specification. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Stratix 10 FPGA H-Tile Hard IP for Ethernet Key Features The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets Offering Brief No No No Yes Encrypted Verilog Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes Offering Brief Production a1JUi0000049UV0MAM What's Included Encrypted Verilog source code Ordering Information IP-ETH-HTILEHIP; IP-ETH-HTILEKRCR Digikey Mouser a1JUi0000049UV0MAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2026-04-21T12:58:34.000+0000 The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation. Altera Solutions