Why aren't my delay chain values back-annotated correctly? - Why aren't my delay chain values back-annotated correctly? Description Due to a problem in the Quartus® II software version 12.1 and later, back-annotation of delay chain settings does not work correctly. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices. Resolution To work around this problem, back annotate delay chain settings using a Tcl script such as the one below. This Tcl script uses D5 delay chain settings as an example. load_package chip_planner project_open <project_reversion_name> read_netlist set nodes [get_nodes -type io] foreach_in_collection node { set name [get_node_info -info name -node ] set d5 [get_node_info -info "D5 Delay Chain" -node ] if { != 0 } { set_instance_assignment -name T9_DELAY -to } } project_close Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']