Spectra-Q Timing Analyzer Might Apply TimeQuest Deration Incorrectly to Designs with the set_timing_derate Assignments Targeting Blocks with Minimum Period or Pulse Width Limits - Spectra-Q Timing Analyzer Might Apply TimeQuest Deration Incorrectly to Designs with the set_timing_derate Assignments Targeting Blocks with Minimum Period or Pulse Width Limits Description For Arria ® 10 and Cyclone® 10 designs, If you apply the set_timing_derate Tcl command to blocks with minimum period or minimum pulse width limits, Spectra-Q TimeQuest might apply the timing deration to your design incorrectly. This issue affects the Quartus ® Prime Standard Edition software and the Quartus Prime Pro Edition software. Resolution Run Spectra-Q Timing Analyzer with the force_dat option: Run quartus_sta -force_dat from the command line. Run create_timing_netlist -force_dat from the Spectra-Q TimeQuest GUI. Custom Fields values: ['novalue'] Troubleshooting FB: 493284; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 16.1 16.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25