Multi-rate Ethernet valid signal behavior - Multi-rate Ethernet valid signal behavior I'm working with the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core on an Arria V device. https://www.intel.com/content/www/us/en/docs/programmable/683171/current/introduction-to-the-protocol-specific.html#joc1445401896251 I fixed my IP to 2.5G and have a question about the gmii16b_rx_dv signal. The datasheet explains that this signal marks which of the 2 bytes are valid: Is it possible for one of the bits of gmii16b_rx_dv to be '0' in the middle of a packet ? Or it can happen ONLY in the last byte ? Replies: Re: Multi-rate Ethernet valid signal behavior I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you. Regards, Pavee Replies: Re: Multi-rate Ethernet valid signal behavior Hello, Good day. The lower byte (gmii16b_rxd[7:0]) contains the valid data. Hope this answer your query. Regards, Pavee Replies: Re: Multi-rate Ethernet valid signal behavior Thanks for the input. When it does happen, which of the bytes will contain valid data [15:8] or [7:0] ? Replies: Re: Multi-rate Ethernet valid signal behavior Hello, It can happen only in the last word of a packet. In the middle of a packet, both bits of gmii16b_rx_dv should always be '1'. Hope this answer your query. Regards, Pavee