Arria 10 PAC qsf top example - Arria 10 PAC qsf top example Hi, I have in my pc (windows) an Arria 10 PAC. I would like to program it with Quartus Prime Pro (JTAG) as a normal FPGA and not use the Acceleration Stack for Intel or AFU . I am searching for an example .qsf design file for the port connections, since I cannot find in the documentation which pins are used for the clocks and PCIe Hard IP are connected to. I just want to test a small PCIe example. I appreciate the help, thanks. Replies: Re: Arria 10 PAC qsf top example it is ok, thanks Replies: Re: Arria 10 PAC qsf top example Hi, the info you request is not available and it is confidential, as the Arria 10 PAC card is created for acceleration platform and flow.