DDR2 and DDR3 SDRAM Controller with UniPHY Simulation Fails in Riviera - DDR2 and DDR3 SDRAM Controller with UniPHY Simulation Fails in Riviera
Description Simulations with the Riviera software fail. Resolution To work around this issue, modify the following lines in rand_burstcount_gen.sv � outside of the generate block:� localparam MIN_EXPONENT= ceil_log2(MIN_BURSTCOUNT);� localparam MAX_EXPONENT= log2(MAX_BURSTCOUNT);� localparam EXPONENT_WIDTH= ceil_log2(MAX_EXPONENT);
Custom Fields values:
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Troubleshooting
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True
['Simulation']
['FPGA Dev Tools Quartus II Software']
12.0
10.0
['Programmable Logic Devices']
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['novalue']
['novalue'] - 2021-08-25
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