Do DDR5 or LPDDR5 memory interfaces for Intel Agilex® 5 and Intel Agilex® 7 FPGA devices support mailbox commands to all channels for multichannel instances? - Do DDR5 or LPDDR5 memory interfaces for Intel Agilex® 5 and Intel Agilex® 7 FPGA devices support mailbox commands to all channels for multichannel instances? Description For Intel Agilex® 5 FPGA and Intel Agilex® 7 FPGA in Intel® Quartus® Prime Pro Edition Software version 23.3, DDR5 2x16 and LPDDR5 2x16 EMIF IP mailbox command " GET_MEM_INTF_INFO " returns 1. All mailbox commands can only access CH1 of the interface. Resolution This feature enhancement is available beginning with Intel® Quartus® Prime Pro Edition Software version 23.4 Custom Fields values: ['novalue'] Troubleshooting 14020415053 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 23.4 23.3 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']