BARs must be disabled when using Root Port - BARs must be disabled when using Root Port Description You will see this message if you have enabled Base Address Registers (BARs) for the Avalon Memory-Mapped (Avalon-MM) of the Altera® Hard IP core for PCI Express® with Port type set to Native Endpoint, but then switch to Port type Root Port. For example: 1) Enable BAR0 (32-bit non prefetchable) 2) Enable BAR1 (32-bit non prefetchable) 3) Change the Port Type from Native endpoint to Root port Resolution To work around this issue: Re-select the Endpoint type, disable all BARs, then re-select Root Port type. This behavior is not scheduled to be changed in a future Quartus® II software version. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']