Why does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10? - Why does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2 and later, the Multi-Channel DMA FPGA IP for PCI Express* may stall or cease operation when the Q_SIZE parameter is set to 0x10. Resolution The recommended workaround is to limit Q_SIZE to 0xF. If your design requires a Q_SIZE of 0x10, upgrade to the Quartus® Prime Pro Edition software version 25.3.1, regenerate the Multi-Channel DMA FPGA IP for PCI Express, and recompile the design to ensure the fix takes effect. Custom Fields values: ['novalue'] Troubleshooting 15018818083 novalue ['novalue'] ['novalue'] 25.3.1 24.2 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']