How can I speed up the simulation time of the PCI Express Hard IP? - How can I speed up the simulation time of the PCI Express Hard IP? Description You can set test_in[0] on the PCI Express® DUT model to “1” to accelerate the MegaCore® function initialization counters. Also, y ou must set the rp_test_in[0] on the BFM Root Complex to “1” if using the testbench and BFM Root Complex. The simulation can also be speeded up by modifying the following testbench VHDL generics/Verilog HDL parameters: a) set "FAST_COUNTERS" to "1" to make the timing counters in the PCIe® core operate faster. b) set “PIPE_MODE_SIM” to "1" to enable PIPE as opposed to serial mode simulation in the testbench. Related Articles Why is my PCI Express core's tx_out always HiZ during simulation? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA'] ['novalue'] ['novalue'] ['novalue']