AVY ERROR: TS2 symbol6 bit[6] (Quiesce Guarantee) is asserted while TS2 symbol6 bit[7] (Request Equalization) is deasserted, expectation is that both bits need to be asserted at the same time - AVY ERROR: TS2 symbol6 bit[6] (Quiesce Guarantee) is asserted while TS2 symbol6 bit[7] (Request Equalization) is deasserted, expectation is that both bits need to be asserted at the same time Description You may observe the following error message when simulating the P-Tile Avalon® Streaming FPGA IP for PCI Express* with the Avery BFM in the Synopsys* VCS* or VCS MX software. " AVY ERROR: TS2 symbol6 bit[6] (Quiesce Guarantee) is asserted while bit[7] (Request Equalization) is deasserted. Both bits are expected to be asserted simultaneously. " Resolution This error message can be safely ignored. Quiesce Guarantee bit is ignored when Request Equalization bit is deasserted. Custom Fields values: ['novalue'] Troubleshooting 15017866540 False ['P-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']