Creating Reusable Design Blocks: IP Integration with the Altera® Quartus® Prime Software - Same Course in Japanese: 再利用可能なデザイン・ブロックの生成方法：Quartus IIソフトウェアを使用したIPの統合 16 Minutes This training is part 3 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training discusses how best to create your IP so it will easily integrate into a design in the Altera® Quartus® Prime software. It also presents final aspects of the IP design process, such as documentation and creating a GUI interface using the Platform Designer Component Editor. The training also includes an IP development checklist to help manage everything needed for distributing your IP. Course Objectives At course completion, you will be able to: Follow design recommendations for easy integration into the Altera® Quartus® Prime software Provide useful documentation for your IP Create a GUI interface for your IP using the Platform Designer Component Editor Skills Required Background in digital logic design Familiarity with an HDL language (Verilog or VHDL) Familiarity with the Altera® Quartus® Prime software Familiarity with Tcl scripting Some familiarity with SDC timing constraints If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OIPR1002. FPGA_OIPR1002. <p>Creating Reusable Design Blocks: IP Integration with the Altera Quartus Prime Software</p>