Why is the ROM Fmax of Intel Stratix 10 device family reported by Timing Analyzer different from the datasheet? - Why is the ROM Fmax of Intel Stratix 10 device family reported by Timing Analyzer different from the datasheet? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.4 and earlier, The ROM Fmax in Compilation Report > Timing Analyzer > Slow 900mV 100C Model > Fmax Summary is different from the Intel® Stratix® 10 Device Datasheet . For example, in the Intel® Stratix® 10 Device Datasheet page34, Table 31 Memory Block Performance Specification for Intel Stratix 10 Devices shows the ROM(MLAB) performance is 667MHz for -E3V device while these is reported as "400MHz" in Intel® Quartus® Prime Pro Edition software version 19.4 and eariler. Resolution Please refer to the Intel® Stratix® 10 Device Datasheet for the correct specification. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507804377 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']