xSPI-MC: xSPI, HyperBus™, and Xccela™ Serial Memory Controller - The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection,… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it. The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards. The core allows the system to interface with one or more serial memory devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in Access In-Place (AIP) mode where the core allows the system to directly access the SPI memory address space via an AHB or AXI slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM, or DRAM) using its AHB master interface. xSPI-MC can work with single, dual, quad, twin-quad, octal or 16x SPI memory devices. To enable use with memory devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers, and b) by using the auto-configuration feature, where the core will autonomously identify the connected memory device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features. The xSPI-MC can be easily configured to match different application requirements. The instantiation of the DMA engine and the auto-configuration logic, the maximum number of memory devices that the core supports, and the reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines. The core can be implemented in any ASIC or FPGA technology, as it is delivered with a synthesizable soft-PHY, and does not use any process-specific modules. Sample timing constraints are provided with the core and optional technology mapping support is available. Flash Aerospace Broadcast Consumer Defense Industrial Medical Test Transportation Wireless xSPI-MC: xSPI, HyperBus™, and Xccela™ Serial Memory Controller Key Features Broad Protocol Support – Supports xSPI, HyperBus™, Xccela™, and proprietary SPI interfaces. Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6kMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, FPGA netlist Ordering Information xSPI-MC Direct a1JUi0000049U6kMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T21:01:16.000+0000 The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection, direct boot, and operation in multiple modes: Slave (AHB slave access), DMA (with internal DMA engine), Access In-Place (AIP) via AHB/AXI, and Boot-Image copy after reset. Compatible with single to 16x SPI devices, it offers flexible configuration through registers or an auto-configuration feature using a device list. Highly customizable via Verilog defines, it allows selection of DMA, auto-configuration, and device count. Delivered with a synthesizable soft-PHY, it is FPGA/ASIC ready and requires no process-specific dependencies. Partner Solutions