Rounding error might cause clock edge misalignment in timing analysis - Rounding error might cause clock edge misalignment in timing analysis Description If you use the TimeQuest Timing Analyzer to analyze a design that contains a noninteger phase shift relationship between the launch clock and the latch clock, timing analysis might fail. Rounding errors that occur during timing analysis cause periodic clock edge misalignments. Resolution Avoid specifying a phase shift that is not integrally divisible by the clock period. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']