Why does the F-Tile Architecture and PMA and FEC Direct PHY IP not show any error when configuring with a PMA width of 16b and TX and RX double-width enabled? - Why does the F-Tile Architecture and PMA and FEC Direct PHY IP not show any error when configuring with a PMA width of 16b and TX and RX double-width enabled? Description Due to an error in the F-tile Architecture and PMA and FEC Direct PHY IP, when configuring with a PMA width of 16b and TX and RX double-width enabled you might not see any error message for the wrongly selected configuration in the Quartus® Prime Software version 22.1. The IP wizard doesn't complain and allows you to generate the IP files. During the SLG stage of compilation the following errors will be seen. Error(21843): Conflict 0 ---------------------------------------------------------------- Error(21843): Rule: gdr_wrapper::topology_mapping_mux_rule @ Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577a.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): Rule: gdr_virtual_channel::topo_and_stream_down_to_maib_adapter_tx_and_rx_fifo_mode_and_width_rules @ gdr Error(21843): gdr.z1577a.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == FALSE || gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src != E400G_STREAM15_SYS_CLK_SRC_XCVR || gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode != E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER || gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode != E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP || gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use != E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE || gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width inside {E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32} Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_sys_clk_src_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_sys_clk_src -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.sys_clk_src) != E400G_25G_15_SYS_CLK_SRC_XCVR || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src== E400G_STREAM15_SYS_CLK_SRC_XCVR Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_aib_if_fifo_mode_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_aib_if_fifo_mode -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_aib_if_fifo_mode) != E400G_25G_15_TX_AIB_IF_FIFO_MODE_REGISTER || gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode == E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_enable_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use) == E400G_25G_15_TX_PRIMARY_USE_DISABLED || gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == TRUE Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_excvr_if_fifo_mode_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_excvr_if_fifo_mode -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_excvr_if_fifo_mode) != E400G_25G_15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP || gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode == E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_primary_use_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use) != E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE || gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use == E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_xcvr_width_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_xcvr_width -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_xcvr_width) != E400G_25G_15_TX_XCVR_WIDTH_16 || gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width == E400G_STREAM15_TX_XCVR_WIDTH_16 Error(21843): Input variables: Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ehip_tx[0] -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx Error(21843): is_used == TRUE Error(21843): location == E400G_25G_15 Error(21843): sys_clk_src== SYS_CLK_SRC_XCVR Error(21843): tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_REGISTER Error(21843): tx_en == TRUE Error(21843): tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error(21843): tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE Error(21843): tx_xcvr_width == TX_XCVR_WIDTH_16 The problem is gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width inside {E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32} tx_xcvr_width == TX_XCVR_WIDTH_16 doesn't seem to be allowed. Resolution To work around this problem, ensure that only supported modes are generated, as documented in the PMA Supported Modes section of the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 18023003520 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']