Simulation stalls when global_reset_n is toggled early in Intel® Arria® 10 FPGA DDR4 PHY-Only IP simulation - Simulation stalls when global_reset_n is toggled early in Intel® Arria® 10 FPGA DDR4 PHY-Only IP simulation Description When performing a functional simulation with the Intel® Arria® 10 FPGA DDR4 PHY-Only IP, toggling the global_reset_n early in the simulation might stall the sequencer resulting in afi_cal_success or afi_cal_fail never asserting. This is a problem with simulation only and does not affect the hardware function. Resolution As a workaround, apply a global_reset_n pattern similar to that generated by the altera_avalon_reset_source block in the DDR4 simulation design example. Custom Fields values: ['novalue'] Troubleshooting - False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']