10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design - UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency. Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GS FPGA UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency. Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Defense Industrial Medical Test Transportation 10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design Key Features Highly modular UDP/IP stack implementation in synthesizable HDL Offering Brief No No No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Yes No 25.1.1 Offering Brief Production a1JUi000006PXa1MAG What's Included Modular and application-specific 10G/25G UDP IP Cores, and example design projects Ordering Information npap-udp-10G-25G a1JUi000006PXa1MAG Production Design Services Intellectual Property (IP) a1MUi00000BO8sfMAD a1MUi00000BO8sfMAD Select 2025-12-02T00:49:33.000+0000 UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency. Partner Solutions