Why do I see CRC Error for the Agilex® 5 HPS EMAC when operating at -40°C - Why do I see CRC Error for the Agilex® 5 HPS EMAC when operating at -40°C Description When operating the Agilex® 5 FPGA Device at temperature of -40°C, you may see consistent CRC Error for Hard Processor EMAC, this is due to the uncalibrated IO Delay value for the the EMAC and the PHY. Resolution The IO Delay between the EMAC and PHY would require calibration as the values varies for different board design. Please follow the workflow summary to identify the optimal timing margin: (Applicable to all OPN supporting different voltage and temperature range) Configure Delay: Write the desired delay value to the IO Delay control registers for the Transmit and Receive Clock pins of the RGMII interface. (refer to schematic or design to identify the IO pins) Verify Link: Ensure the Ethernet interface is up (supports 10/100/1000 Mbps). Ethernet Data Transfer Test: Perform a data transfer (e.g., a ping test with a high packet count). Analyze Errors, check for: Packet Loss: Dropped packets during transit. CRC Errors: Integrity issues in the received data. Repeat: Iterate through all possible delay combinations to identify the "passing window". Select: Choose a setting in the center of the passing range to ensure maximum hardware margin. Additional Information For more details or help on the calibration workflow, please contact Altera® technical support . Custom Fields values: ['novalue'] Troubleshooting 15018754804 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']