Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1? - Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?
Description Due to a problem in the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1, you may observe a minimum pulse width timing violation information message during compilation. Resolution This message can be safely ignored. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.1.
Custom Fields values:
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Troubleshooting
FB: 589925;
True
['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express']
['FPGA Dev Tools Quartus® Prime Software Pro']
19.1
18.1
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-30
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