Stratix V Clock Networks Incorrect - Stratix V Clock Networks Incorrect
Description The Quartus II software does not correctly model the timing performance of clock networks in Stratix V ES devices when both edges of the clock signal are used. Affects Stratix V engineering sample devices. Resolution Refer to the Stratix V datasheet for applicable clock frequency limits in this case.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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11.0.1
['Stratix® V FPGAs']
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['novalue'] - 2021-08-25
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