Is there a known problem with the DATA[0] connection shown in the block diagrams for Passive Serial Configuration in the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook? - Is there a known problem with the DATA[0] connection shown in the block diagrams for Passive Serial Configuration in the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook? Description Yes, in Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook version 2020.05.21 and earlier, there is a problem with the DATA[0] connection in the block diagram available in Chapter 6.1.2, Figures 88, 89 and 90. These diagrams incorrectly show a direct connection for DATA[0] between the Intel® Cyclone® 10 LP FPGA and Memory device. Resolution The DATA[0] pin should be connecting to the external host, such as a CPLD or microprocessor, as shown below. This is scheduled to be fixed in future release of the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook Custom Fields values: ['novalue'] Troubleshooting 1508489119 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.2 ['Cyclone® 10 LP FPGA'] ['novalue'] ['novalue'] ['novalue']