Why does the Dual Simplex Example Design in GTS JESD204C FPGA IP, with the data path clocking mode set to System PLL and JESD204C DS wrapper set to “Dual Simplex applied on JESD204C PHY,” fail to generate when the data rate exceeds 10,312.5 Mbps? - Why does the Dual Simplex Example Design in GTS JESD204C FPGA IP, with the data path clocking mode set to System PLL and JESD204C DS wrapper set to “Dual Simplex applied on JESD204C PHY,” fail to generate when the data rate exceeds 10,312.5 Mbps? Description The Dual Simplex Example Design generation fails when the data rate exceeds 10,312.5 Mbps due to a System PLL clock constraint being violated. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3. Custom Fields values: ['novalue'] Troubleshooting 15018300408 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']