How to configure FPGA-to-HPS interface SDRAM direct mode when ECC is turned on in Intel Agilex® 7 SoC device? - How to configure FPGA-to-HPS interface SDRAM direct mode when ECC is turned on in Intel Agilex® 7 SoC device? Description When ECC is turned on in HPS External Memory Interface (EMIF) in Intel Agilex® 7 SoC device, the memory address generates ECC data for both F2H SDRAM direct mode and F2H CCU mode. So it requires that FPGA-to-HPS master use the same memory address with MPU even in FPGA-to-HPS SDRAM direct mode. Otherwise, an ECC error may be triggered. This restriction does not apply when ECC is turned off. Resolution When the FPGA-to-HPS master and MPU master get access to the memory space lower than 2GB, the memory address is used from 0x0000 0000 to 0x7FFF FFFF. When the FPGA-to-HPS master and MPU master get access to the memory space larger than 2GB, MPU uses the alias address defined in the DTS file to access these memory addresses. The FPGA-to-HPS master must use the same alias address instead of the physical address for both F2H SDRAM direct mode and F2H CCU mode. Here is the example of 4GB HPS EMIF in an Intel Agilex® 7 SoC device: In DTS, memory is defined into two regions, as shown below. Then FPGA-to-HPS master and MPU must use an address from 0x1080000000 to 0x10FFFFFFFF to access the 2GB ~ 4GB memory space. memory { reg = <0 0x00000000 0 0x80000000>, <0x10 0x80000000 0 0x80000000>; }; To enable access to the full 4GB memory space with the above alias address, the following registers should also be set accordingly. You can set these registers in the uboot file uboot-socfpga\arch\arm\mach-socfpga\spl_agilex.c writel(0x100000, 0xF8020110); // region0addr_base writel(0x0, 0xF8020114); // region0addr_baseext writel(0xFFFFFFFF, 0xF8020118); // region0addr_limit (lower 32bits) writel(0x10, 0xF802011C); //region0addr_limitext (upper 32bits) writel(0x1, 0xF8020104); //enable_set for regions Custom Fields values: ['novalue'] Troubleshooting 15010767220, 15010963454 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 21.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']