Why do I see incorrect transceiver dynamic reconfiguration behavior when using Quartus® II software version 14.1 of the Native PHY IP core for Intel® Arria®10 devices? - Why do I see incorrect transceiver dynamic reconfiguration behavior when using Quartus® II software version 14.1 of the Native PHY IP core for Intel® Arria®10 devices? Description Due to a bug in Quartus® II software version 14.1 you may see incorrect transceiver dynamic reconfiguration behavior of channels other than channel 0 of an Arria® 10 device, multi-channel Native PHY IP core when the Share reconfiguration interface option is disabled. When the Share reconfiguration interface option is disabled, the reconfig_writedata port of channel 0 is erroneously applied to all channels of the Native PHY IP core. Resolution To work around this problem you can enable the Share reconfiguration interface option in the Native PHY IP core. This problem will be fixed in a future version of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']