Intel OneApi and Stratix 10 GX MMD MMD JTag problem - Intel OneApi and Stratix 10 GX MMD MMD JTag problem Hello, I have problems testing programs of Intel(R) oneAPI DPC++ Compiler 2021.1 (2020.8.0.1005) for FPGAs with Quartus 19.4 support for a custom platform: Stratix10 GX with Quartus 19.4 BSP. After compilation, I run the program and It try to reprogram the Stratix10GX, but one of the messages shows "Autodetect Cable not Found" MMD INFO : [acls10_ref0] Trying Full-Chip Reconfiguration (JTAG) MMD INFO : Autodetect Cable not found!! MMD INFO : setting Cable to default value 1 MMD INFO : setting Device Index to default value 1 MMD INFO : executing "quartus_pgm -c 1 -m jtag -o "P;reprogram_temp.sof@1"" As the default jtag chain is 1, the IDs do not correspond to the FPGA chip and the programming fault. For my device jtag chain is : 1) USB-BlasterII [5-4] 020A40DD 5M(1270ZF324|2210Z)/EPM2210 C32150DD 1SG280HH(1S2|2S2|3S2)/.. and the programming error is as below: Error (18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xC32150DD for device 1, but found JTAG ID code 0x020A40DD. Error (209012): Operation failed If I try to test an OpenCL program and run it after "aocl program *.aocx" it is successful. How I can program the FPGA with OneApi? I had tested three examples: fpga_compile, loop_unrool, and max_concurrency(this worked for me the first time that I run, and never again). I appreciate your kindle help Replies: Re: Intel OneApi and Stratix 10 GX MMD MMD JTag problem Hi , Hope the community discussion was useful and the issue is resolved. Just to add on please find the knowledge base link below for similar JTAG errors https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd01172013_21.html Thanks and Regards Anil Replies: Re: Intel OneApi and Stratix 10 GX MMD MMD JTag problem Typically you would program the FPGA via JTAG once and after that, run-time reconfiguration should happen via PCI-E. You can manually reconfigure the FPGA via JTAG by using the following chain of commands to extract the .sof from your .aocx file (replace text between ** with appropriate names): aocl binedit *aocx_file* get .acl.fpga.bin *bin_file* aocl binedit *bin_file* get .acl.sof *sof_file* And then run quartus_pgm to program the FPGA (@2 points to the second device in the JTAG chain): quartus_pgm --mode=JTAG --cable=1 -o "p;*sof_file*;@2" Then do a reboot and after that PCI-E-based reconfiguration should work if your BSP has been created correctly.