Why might I see a poor Bit Error Rate (BER) after performing dynamic reconfiguration of the Native PHY IP using the embedded streamer of a Stratix® 10 E-Tile device in Quartus® Prime software version 18.0? - Why might I see a poor Bit Error Rate (BER) after performing dynamic reconfiguration of the Native PHY IP using the embedded streamer of a Stratix® 10 E-Tile device in Quartus® Prime software version 18.0? Description Due to a bug in Quartus Prime software version 18.0, the Tx pre-emphasis settings are not included in the Stratix 10 E-Tile device Native PHY IP embedded streamer dynamic reconfiguration files. Resolution To work around this problem you can perform a manual Avalon Memory Mapped interface write to the transmitter pre-emphasis Native PHY PMA registers after running the embedded streamer dynamic reconfiguration process. This problem will be fixed in a future version of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 565064; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']