Syntax error in initial block - Syntax error in initial block I am using Quartus Prime Lite Edition v22.1.1 In my Verilog HDL code, I include the following initial block: initial begin div = 4’b0; lpc = 4’b0; pa = 4’b0; plc_lsb = 8’b0; plc_usb = 8’b0; dsb = 9’b0; end A syntax error in every line of the initial block is generated when I compile the code. I do not see anything wrong with the code though. Replies: Re: Syntax error in initial block As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘ https://supporttickets.intel.com’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey Replies: Re: Syntax error in initial block Let me know if you manage to resolve the issue Replies: Re: Syntax error in initial block Thanks a lot. That is indeed the problem. I have no idea how that back tick crept in as I do not have it on my keyboard. Perhaps I copied it from somewhere though I cannot remember. Replies: Re: Syntax error in initial block Ok, I think I found the problem. I copied your code via cut/paste and it barfs when I compile. It appears in your constants in the initial block you used a unicode apostrophe character instead of a single ascii apostrophe ('). At least that is what I got when I did a cut/paste of your code verbatim. Once I went in and edited the constants to use a single ascii apostrophe (ie, like 4'b0) it compiled Ok. foo.c is your code. The apostrophe character in the constants is '342 200 231' instead of the single ascii apostrophe (') in the edited code bar.c. par[533] od -c foo.v 0000000 i n i t i a l b e g i n \r \n d 0000020 i v = 4 342 200 231 b 0 ; \r \n l p 0000040 c = 4 342 200 231 b 0 ; \r \n p a 0000060 = 4 342 200 231 b 0 ; \r \n p l c _ l 0000100 s b = 8 342 200 231 b 0 ; \r \n p l 0000120 c _ u s b = 8 342 200 231 b 0 ; \r 0000140 \n d s b = 9 342 200 231 b 0 ; \r \n 0000160 e n d \r \n 0000165 par[536] par[536] od -c bar.v 0000000 i n i t i a l b e g i n \r \n d 0000020 i v = 4 ' b 0 ; \r \n l p c 0000040 = 4 ' b 0 ; \r \n p a = 4 ' 0000060 b 0 ; \r \n p l c _ l s b = 8 0000100 ' b 0 ; \r \n p l c _ u s b = 0000120 8 ' b 0 ; \r \n d s b = 9 ' b 0000140 0 ; \r \n e n d \r \n Replies: Re: Syntax error in initial block The error messages for each line within the initial block are: Error (10170): Verilog HDL syntax error at dsb.v(10) near text: . Check for and fix any syntax errors that appear immediately before or at the specified keyword. Error (10170): Verilog HDL syntax error at dsb.v(10) near text: " "; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. Code before the initial block is: module dsb (clk_c, plc_lsb, plc_usb, dsb); input clk_c; output plc_lsb, plc_usb, dsb; reg [3:0] div, lpc, pa; // div = counter used to obtain clk_m from clk_c wire [3:0]sub, add; reg [7:0] plc_lsb, plc_usb; reg [8:0] dsb; initial begin div = 4’b0; lpc = 4’b0; pa = 4’b0; plc_lsb = 8’b0; plc_usb = 8’b0; dsb = 9’b0; end Replies: Re: Syntax error in initial block You need to provide more info. What exactly is the error message(s) that are being generated? What is the code context of the initial block (ie, the verilog code before the block). Guessing it could be the initial block is not valid in that context, or the items you assign in the block are not reg variables.