Why does the GTS SDI II IP observe a Single Rate (SR) Dual Simplex (DS) port failure when migrating from an older version of the SR DS Design Example to Quartus® Prime Pro Edition Software version 25.1? - Why does the GTS SDI II IP observe a Single Rate (SR) Dual Simplex (DS) port failure when migrating from an older version of the SR DS Design Example to Quartus® Prime Pro Edition Software version 25.1? Description Due to a problem in the Quartus Prime Pro Edition software version 25.1, you may observe the Dual Simplex(DS) port failure in GTS SDI II IP when migrating an SR DS design generated by a former version to the Quartus Prime Pro Edition software version 25.1. This is because the Dual Simplex port name changes. Resolution To work around this problem, modify the GTS SDI top level file (sdi_ii_agi_demo.sv) in example_design/rtl/ path. Example: SDI II Wrapper = Both Base and PHY sdi_rx_inst0_auto _rx_cdr_refclk -> rx_cdr_refclk_ sdi_rx_inst0 SDI II Wrapper = Base only dphy_rx_inst0_auto _i_rx_cdr_refclk_p -> i_rx_cdr_refclk_p_ dphy_rx_inst0 Additional Information This list of port name changes can be found in this link . Custom Fields values: ['novalue'] Errata 15017393091, 15017408576 False ['SDI II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']