Warning (332174): Ignored filter at *_altera_stratix10_interface_generator_*.sdc(3): emac_ptp_ref_clock_clk could not be matched with a port. - Warning (332174): Ignored filter at *_altera_stratix10_interface_generator_*.sdc(3): emac_ptp_ref_clock_clk could not be matched with a port. Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3 or earlier, you may see the following warning message when enabling the emac_ptp_ref_clock_clk pin in the HPS of the Intel® Stratix® 10 device: Warning(332174): Ignored filter at *_altera_stratix10_interface_generator_*.sdc(3): emac_ptp_ref_clock_clk could not be matched with a port. Resolution To work around this problem, please use the timing constraint like the following description: create_clock -period <period value> -name <clock_name> [get_ports {target emac_ptp_ref_clock_clk name}] This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 1509852909 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 19.3 ['Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']