Why is the o_rx_pcs_ready of the F-Tile Ethernet FPGA IP not asserted in PAM4 cases with PMA REFCLK set as 312.5MHz variants fail with PCS ready low when VSR assignment is enabled in the design QSF? - Why is the o_rx_pcs_ready of the F-Tile Ethernet FPGA IP not asserted in PAM4 cases with PMA REFCLK set as 312.5MHz variants fail with PCS ready low when VSR assignment is enabled in the design QSF? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, the o_rx_pcs_ready of the F-Tile Ethernet IP is not asserted in PAM4 cases with PMA REFCLK set as 312.5MHz variants fail with PCS ready low when VSR assignment is enabled in the design QSF. Resolution To work around this problem, disable the VSR assignment in the design QSF. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16019784620 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']