In which clock domain of the Arria 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core are the following signals, led_link, led_char_err, led_disp_err, and led_an. - In which clock domain of the Arria 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core are the following signals, led_link, led_char_err, led_disp_err, and led_an. Description The clock domain of led_link , led_char_err , led_disp_err , and led_an signals for the Arria® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core is an internal clock domain. Because you cannot use the internal clock in the FPGA fabric, these led_* signals need to be treated as asynchronous signals. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25