Why does my RAM inference fail for Stratix 10 designs? - Why does my RAM inference fail for Stratix 10 designs? Description In the Quartus® Prime Pro edition software, you may see that RAMs that were inferred as M20Ks in Stratix® V or Arria® 10 are not inferred in Stratix 10 for one of the following reasons: Stratix 10 does not support True Dual Port (TDP) dual clock RAMs Stratix 10 does not support mixed width TDP RAMs Stratix 10 does not support "old data" mixed port read-during-write(RDW) behaviour for TDP RAMs Stratix 10 only supports mixed width simple dual port (SDP) RAMs with ratios of 1:2 and 1:4 (1:8, 1:16 and 1:32 are not supported) Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue novalue ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']