The software design constraints (SDC) provided by the 10GBASE-R IP is invalid when the IP is instantiated within the VHDL generate block. - The software design constraints (SDC) provided by the 10GBASE-R IP is invalid when the IP is instantiated within the VHDL generate block. Description When the 10GBASE-R IP is instantiated within the VHDL generate block, the SDC provided by the IP is invalid. This issue affects all VHDL designs that instantiate the IP within the VHDL generate block. Resolution None This issue will be fixed in a future version of the Quartus ® Prime Standard Edition software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']