Clock switchover on CycloneV PLL - Clock switchover on CycloneV PLL Hello all, In a cyclone V device, I'm using a PLL supporting the automatic switchover with manual override. On the 2x clock output, I observe a jump of 2 clock cycles whenever there's a switchover (as if a clock cycle of the 1x input clock is lost). I think this is expected, but I would like to know if there's a ay to overcome this behavior. I tried configuring the PLL as Low Bandwidth, but it didn't help. Any idea? Thanks a lot in advance for your support! Replies: Re: Clock switchover on CycloneV PLL It would take 2-3 clock cycles to detect the stopped clock: This is not mentioned in the document. another 2-3 clock cycles to complete the switch: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/ip-core-parameters-clock-switchover-tab.html the circuit automatically switches to the backup clock in a few clock cycles a couple of cycles extra until the PLL achieves lock: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/pll-lock.html The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal. The Max Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) is 1 ms based on this https://www.intel.com/content/www/us/en/docs/programmable/683801/current/pll-specifications.html Replies: Re: Clock switchover on CycloneV PLL ShengN_altera : thanks for the clarification, is there any documentation clarifying all this information? (also about the locked behavior) Does the locked signal from the PLL behave accordingly? Replies: Re: Clock switchover on CycloneV PLL Yes, if based on this internal message: It would take 2-3 clock cycles to detect the stopped clock , another 2-3 clock cycles to complete the switch and a couple of cycles extra until the PLL achieves lock . Replies: Re: Clock switchover on CycloneV PLL Hi ShengN_altera thanks for your reply. "... the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk" This means that input circuit needs some clock cycles to detect that one of the input is now missing: fine. In consequence of that event, do the PLL outputs also stops working for the same amount of clock cycles? For better understanding, the two input clocks have the same frequency. Replies: Re: Clock switchover on CycloneV PLL Let me know if further assistance is needed for this thread? Replies: Re: Clock switchover on CycloneV PLL Please ignore previous post, check this link the PLL circuitry monitors the selected reference clock. If one clock stops, the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk. Based on the internal message, those few clock cycles can't be avoided and usually take about 2-3 cycles. Replies: Re: Clock switchover on CycloneV PLL [Deleted]