Why do I see generation error message when generating F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Example Design using Intel® Quartus® Prime Pro Edition software version 23.4 for Windows*? - Why do I see generation error message when generating F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Example Design using Intel® Quartus® Prime Pro Edition software version 23.4 for Windows*? Description Due to a problem with Intel® Quartus® Prime Pro Edition software version 23.4 for Windows*, you may see the below error message when generating F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Example Design. Error: error deleting "<User Directory>/alt9760_7258718282910928946.dir/0001_pcie_avst_f_0_gen//pcie_ed_rp/pcie.qsf": permission denied while executing "__altera__safe_file delete -force -- <User Directory> /alt9760_7258718282910928946.dir/0001_pcie_avst_f_0_gen//pcie_ed_rp/pcie.qsf" ("uplevel" body line 1) invoked from within "uplevel 1 [list __altera__safe_file {*}$args]" (procedure "file" line 2) invoked from within "file delete -force -- "${ORI_TEMP_PATH}/pcie_ed_rp/pcie.qsf"" (procedure "::intel_pcie_ftile_ast::generate_design_example_files" line 367) invoked from within "::intel_pcie_ftile_ast::generate_design_example_files ${QSYSTemPath} ${QSYSTemName} $TEMPPATH" (procedure "::intel_pcie_ftile_ast::generate_dynamic_qsys" line 930) invoked from within "::intel_pcie_ftile_ast::generate_dynamic_qsys" (procedure "::intel_pcie_ftile_ast::dynamic_example_design" line 10) invoked from within "::intel_pcie_ftile_ast::dynamic_example_design" (procedure "::intel_pcie_ftile_ast::fileset::callback_example_design" line 2) invoked from within "::intel_pcie_ftile_ast::fileset::callback_example_design pcie_avst_f_0_example_design" Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15015269361 False ['F-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']