Error(19261): Signal pcie_rstn_pin_perst has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST. - Error(19261): Signal pcie_rstn_pin_perst has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST. Description The following error will be seen when compiling a design that includes the Intel® Stratix® 10 Hard IP for PCI Express targeting an 1SG040* device OPN. The nPERSTL0 pin of this device package is a dual purpose and located in a 3.0 V bank. Error(19261): Signal pcie_rstn_pin_perst has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST. Resolution When using this pin as PCI Express nPERST with I/O standards of 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.0 V LVTTL, the following assignment should be added in the Intel® Quartus® Prime Software settings file (.qsf) to disable GPIO usage and to resolve the error. set_instance_assignment -name USE_AS_3V_GPIO ON -to pin_name Example: set_instance_assignment -name USE_AS_3V_GPIO ON -to pcie_rstn_pin_perst This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 22010780831, 1508838252 False ['Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 19.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']