Internal Error: Sub-system: LVDS, File: /quartus/periph/lvds/lvds_gen6.cpp, Line: 787 - Internal Error: Sub-system: LVDS, File: /quartus/periph/lvds/lvds_gen6.cpp, Line: 787 Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, you may see the internal error above at Fitter stage when there is a PLL connected to multiple LVDS IPs with outclk channel in the same IO bank. This problem only affects Intel® Arria® 10 devices. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 1508714292 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.3 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']